1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus which selectively uses pads.
2. Related Art
In general, expensive test equipment is used to perform a reliability test for a semiconductor memory apparatus. The test is very time-consuming. A high-integration trend of semiconductor memory apparatuses increases a time and cost required for such a test. Therefore, when such a semiconductor integrated circuit test is performed, a plurality of semiconductor integrated circuits is tested simultaneously in parallel to reduce the test time. In this case, input and output pins of a tester are allocated depending on a configuration of the tested semiconductor integrated circuits. However, the limited number of input and output pins of the tester may limit the number of semiconductor integrated circuits which may be tested in parallel. Accordingly, the number of semiconductor integrated circuits to be tested simultaneously may be limited. Also, a semiconductor integrated circuit may be provided with multiple input and output pins. Accordingly, the number of semiconductor integrated circuits to be tested simultaneously is inevitably further limited. Then, since the efficiency of the simultaneous test is reduced by the limited resource of the tester, the test time may increase.